Gigabit Ethernet Link Aggregator Reference Design (TIDA-00269)
The Gigabit Ethernet Link Aggregator reference design features the TLK10081 device which is a multi-rate link aggregator intended for use in high-speed bi-directional point-to-point data transmission systems to reduce the number of physical links by multiplexing lower speed serial links into higher speed serial links. This reference design helps customers reduce the number of serial links that need to be implemented and managed within an application. TLK10081 enables customers to aggregate and de-aggregate multiple serial links, of all types including raw data types. Also, featured is the CDCM6208 device that can provide extremely low-jitter Clock input to the TLK10081 in customer systems that do not have one available (or does not meet the jitter requirement of the system). The high-speed signals of channel A have been routed to SFP+ modules for easy evaluation in systems that implement optical fiber configurations. The high-speed signals of channel B have been routed to edge launch SMA connectors for easy evaluation in systems that use standard test equipment.
TLK10081 has the ability to handle many different data types without the need encode the data in a special way. Some common signals include 1 GbE, SGMII, as well as raw data signals at rates from 250 Mbps to 1.25 Gbps 8 × (0.25 to 1.25 Gbps) to 1 x (2 to 10 Gbps) Multiplexing Supports flexible clocking schemes including externally-jitter-cleaned clock recovered from the high-speed side Lowest power consumption per channel (800mW Nominal/Ch) Link aggregation helps reduce cables or routing traces within a system through multiplexing lower speed serial signals into a single high speed serial link Use TLK10081 for de-aggregation on the recieve side of the system
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