16-Bit, 300 kSPS, Low Power Data Acquisition System Optimized for Sub-Nyquist Input Signals Up to 4 kHz (cn0305)
The circuit shown in Figure 1 is a 16-bit, 300 kSPS successive approximation analog-to-digital converter (ADC) system that has a drive amplifier that is optimized for a low system power dissipation of 10.75 mW for input signals up to 4 kHz and sampling rates of 300 kSPS.
This approach is highly useful in portable battery powered or multichannel applications, or where power dissipation is critical. It also provides benefits in applications where the ADC is idle most of the time between conversion bursts.
Drive amplifiers for high performance successive approximation ADCs are typically selected to handle a wide range of input frequencies. However, when an application requires a lower sampling rate, considerable power can be saved because reducing the sampling rate reduces the ADC power dissipation proportionally.
To take full advantage of the power saved by reducing the ADC sampling rate, a low bandwidth, low power amplifier is required.
For example, the 80 MHz ADA4841-1 op amp (12 mW at 10 V) is recommended for inputs up to approximately 100 kHz with the AD7988-5 16-bit successive approximation register (SAR) ADC (3.5 mW at 500 kSPS and 2.1 mW at 300 kSPS). The total system power dissipation including the ADR435 reference (4.65 mW at 7.5 V) is 18.75 mW at 300 kSPS.
For input bandwidths less than 4 kHz and sampling rates less than 300 kSPS, the 1.3 MHz OP1177 op amp (4 mW at 10 V) offers excellent signal-to-noise ratio (SNR) and total harmonic distortion (THD) performance and reduces total system power from 18.75 mW to 10.75 mW, which is a 43% power savings at 300 kSPS.
Figure 1. System Circuit Diagram of Low Power OP1177 Amplifier Driving the AD7988-5 ADC (Simplified Schematic: All Connections Not Shown)
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