Терраэлектроника

EtherCAT(R) Master Reference Design for Sitara AM57x Processor Gb Ethernet and PRU-ICSS (TIDEP0079)

The TIDEP0079 reference design demonstrates an EtherCAT® master interface running on the Sitara™ AM572x processor using the EC-Master stack from acontis. This EtherCAT master solution can be used for EtherCAT-based PLC or motion control applications. EtherCAT master is profiled on both the Ethernet switch and the PRU-ICSS Ethernet ports of the AM572x processor to give designers flexibility to use any of the two switch ports or four PRU-ICSS Ethernet ports on the device. The EtherCAT master implementation can achieve less than 100µs cycle times for both the switch and the PRU-ICSS Ethernet ports.

Возможности

Examples for implementing EtherCAT master on both the Ethernet switch (CPSW) and the PRU-ICSS Ethernet ports for design flexibility Highly portable acontis EC-Master stack Cycle CPU consumption of less than 30µs is achieved for both the Ethernet switch and PRU-ICSS Ethernet ports EtherCAT class A or class B master stack according to ETG.1500 specification This reference design is tested on the TMDXIDK5728 board and includes documentation, software, demo application, and HW design files

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EtherCAT(R) Master Reference Design for Sitara AM57x Processor Gb Ethernet and PRU-ICSS TIDEP0079

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