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SPI Master with Signal Path Delay Compensation Reference Design (TIDEP0033)

The Programmable Real-time unit within the Industrial Communication Subsystem (PRU-ICSS) enables customers to support real-time critical applications without using FPGAs, CPLDs or ASICs. This TI design describes the implementation of the SPI master protocol with signal path delay compensation on PRU-ICSS. It supports the 32-bit communication protocol of ADS8688 with a SPI clock frequency of up to 16.7MHz.


SPI master protocol with adjustable signal path delay compensation (not requiring external hardware for signal path delay compensation) Up to 16.7MHz SPI clock Supports ADS8688 SPI communication protocol Automatic measurement of signal path delay for known slave response This PRU-ICSS firmware has been validated with TIDA00164 (ADS8688 and ISO7141CC) and contains firmware source code, implementation description and getting started instructions.


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SPI Master with Signal Path Delay Compensation Reference Design TIDEP0033

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