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A 16-Bit, 6 MSPS SAR ADC System with Low Power Input Drivers and Reference Optimized for Multiplexed Applications (CN0307)
The circuit in Figure 1 is a 16-bit, 6 MSPS, successive approximation (SAR) analog-to-digital converter (ADC) and differential-to-differential driver combination optimized for low noise (signal-to-noise ratio [SNR] = 88.6 dB) and low distortion (total harmonic distortion [THD] = −110 dBc) at low power. The circuit is ideal for high performance multiplexed data acquisition systems, such as portable digital x-ray systems and security scanners, because the SAR architecture can sample without the latency or pipeline delay typically incurred with pipeline ADCs. The 6 MSPS sampling rate allows fast sampling of multiple channels, and the ADC has true 16-bit dc linearity performance and a serial low voltage differential signaling (LVDS) interface for low pin count and low digital noise.
Figure 1. The ADA4897-1 Driving the AD7625 (All Connections and Decoupling Not Shown)
The driver uses two low noise (1 nV/√Hz) ADA4897-1 op amps that maintain the dynamic performance of the AD7625 ADC at low power levels (3 mA per amplifier). The fast settling time (45 ns to 0.1%) of ADA4897-1 makes them ideal for multiplexed applications.
This combination offers industry-leading dynamic performance at low power in a small board area with the AD7625 in a 5 mm × 5 mm, 32-lead LFCSP; the ADA4897-1 in an 8-lead SOIC; and the AD8031 in a 5-lead SOT-23 package.
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