16-Bit, 100k SPS Low Power Data Acquisition System Optimized for Sub-Nyquist Input Signals Up to 1 kHz (CN0306)
The circuit shown in Figure 1 is a 16-bit, 100 kSPS successive approximation analog-to-digital converter (ADC) system that has a drive amplifier that is optimized for a low system power dissipation of 7.35 mW for input signals up to 1 kHz and sampling rates of 100 kSPS.
This approach is highly useful in portable battery powered or multichannel applications, or where power dissipation is critical. It also provides benefits in applications where the ADC is idle most of the time between conversion bursts.
Drive amplifiers for high performance successive approximation ADCs are typically selected to handle a wide range of input frequencies. However, when an application requires a lower sampling rate, considerable power can be saved because reducing the sampling rate reduces the ADC power dissipation proportionally.
To take full advantage of the power saved by reducing the ADC sampling rate, a low bandwidth, low power amplifier is required. For instance, the 80 MHz ADA4841-1 op amp (12 mW at 10 V) is recommended for operation with the AD7988-1 16-bit successive approximation register (SAR) ADC (0.7 mW at 100 kSPS). The total system power dissipation including the ADR435 reference (4.65 mW at 7.5 V) is 17.35 mW at 100 kSPS.
For input bandwidths up to 1 kHz and sampling rates of 100 kSPS, the 3 MHz AD8641 op amp (2 mW at 10 V) offers excellent signal-to-noise ratio (SNR) and total harmonic distortion (THD) performance and reduces total system power from 17.35 mW to 7.35 mW, which is a 58% power savings at 100 kSPS.
Figure 1. System Circuit Diagram of Low Power AD8641 Amplifier Driving the AD7988-1 ADC (Simplified Schematic: All Connections Not Shown)
Схемы и диаграммы
Быстро получите общее представление о схемотехнике решения
Печатные платы и ПО
Ускорьте разработку по готовому дизайну