High Performance 65 MHz Bandwidth Quad IF Receiver with Antialiasing Filter and 184.32 MSPS Sampling Rate (CN0259)
The circuit, shown in Figure 1, is a 65 MHz bandwidth receiver front end based on the ADL5565 ultrahigh dynamic range differential amplifier driver and the 11-bit, 200 MSPS AD6657A quad IF receiver.
The fourth-order Butterworth antialiasing filter is optimized based on the performance and interface requirements of the amplifier and IF receiver. The total insertion loss due the filter network and other resistive components is only 2.0 dB. The overall circuit has a bandwidth of 65 MHz, with the low-pass filter having a 1 dB bandwidth of 190 MHz and a 3 dB bandwidth of 210 MHz. The pass-band flatness is 1dB.
The circuit is optimized to process a 65 MHz bandwidth IF signal centered at 140 MHz with a sampling rate of 184.32 MSPS. The SNR and SFDR measured with a 140 MHz analog input across the 65 MHz band are 70.1 dBFS and 80.9 dBc, respectively.
Figure 1. Single Channel of Quad IF Receiver Front End (Simplified Schematic: All Connections and Decoupling Not Shown) Gains, Losses, and Signal Levels Measured Values at 10 MHz
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