forward

Материнская плата сервера

Описание:
A 9V-12.6V input, 12W, 90% efficient step-down converter for Server add-on card ASIC core voltage regulation using the TPS53219 PWM Controller and CSD86339Q3D 3x3 Power Block in 264mm2 of total power supply area.

Возможности:

90% Efficiency 264mm2 total power supply area (including PCB area for routing) 2% voltage regulation tolerance <42mV overshoot/undershoot in response to 5A load transient (12VIN) 29 total components for the power supply (including the ICs) Smooth monotonic start up with built-in output discharge (soft stop)

Возможность заказа
  • Заказать BOM
Документация:
  • Схемотехника
  • BOM
  • Тестирование
Описание:
The PMP9703 reference design uses the TPS53915 12A PMBus SWIFT step down converter to provide complete voltage regulation, and system protection of an Enterprise Storage SSD Controller ASIC typically used to control and expand traffic flow in/out of SSDs. The output voltage can be dynamically adjusted in +/- 0.75% steps with a total range of +/-22% of the nominal output voltage (VOUT_ADJUST and VOUT_MARGIN used together) and with programmable step change durations of as little as 4us. The PMBus capability includes adjustment of the typical power supply parameters and monitoring of FAULTs through the STATUS_WORD PMBus command. This PMBus design is ideal for applications that require design flexibility, reduced component count, and Adaptive Voltage Scaling for enhanced performance and optimized power dissipation.

Возможности:

PMBus programming of power supply parameters including output voltage, Power On Delay, Power Good Delay, Soft Start, Switching Frequency and UVLO Integrated 13.8 and 5.9 mΩ MOSFETs With 12-A Continuous Output Current Optimized for ASICs with Adaptive Voltage Scaling (AVS) requirements 335mm2 total power supply area 1.2V output at 12A nominal current 81% efficiency at 12V input, 1.2Vout at 12A

Документация:
  • Схемотехника
  • BOM
  • Тестирование
Описание:
TIDA-00324 is a power reference design that highlights the multiphase controller TPS53631 and the Smart Power Stage CSD95372BQ5M in a 12V Vin, 1.2V Vout at 120A application. This reference design can be used to help a user develop a Power Solution for CPU Vcore power or DDR4 power solution to enable faster development and quicker time to market.

Возможности:

Reference Design for a 12Vin, 1.2Vout, 120A Iout application using a 3-phase controller and Power Stage Complete BOM, schematic, and test data available for the reference design Design can be leveraged for CPU Vcore, DDR Memory Power, or applications needing a multiphase controller plus Power Stage TPS53631 is Intel® VR12.x Platform Serial VID (SVID) Compliant and can operate 1-, 2-, or 3-Phase configuration employing advanced control architecture D-CAP+ with advanced PMBus communication interface for device configurations and system telemetries CSD95372BQ5M smart power stage is a highly optimized design for use in a high-power, high-density applications which integrates the driver IC and power MOSFETs to complete the power stage switching function with accurate current sensing and temperature sensing functionality to simplify system design and improve accuracy

Документация:
  • Схемотехника
  • BOM
  • Тестирование
Описание:
This verified reference design is a PCIe Gen-3 high-speed front-end card design to extend the PCB trace distance of a PCIe sub-system. The board is designed to fit in a x16 lane width PCIe Gen-3 slot between a motherboard and PCIe Gen3 add-in card. This reference design provides users with a useful guideline to incorporate the DS80PCI810 repeater into PCIe Root Complex ASIC and the Add-in Card designs of their own.

Возможности:

PCIe Gen-3 Riser Card compatible to a 16-lane PCIe Gen3 slot from Motherboard Extends PCB trace length of a PCIe Gen-3 sub-system Improves signal Integrity and system robustness Seamlessly compatible with link training between host from Motherboard and End-point card Proven design with compliance test report

Документация:
  • Схемотехника
  • BOM
  • Тестирование
Описание:
This reference design extends the link distance and loss budget of high speed SAS-3 data paths, using configurable equalization, de-emphasis, and output voltage. It supports SAS and SATA interfaces from 1.5 Gbps to 12 Gbps using a miniSAS-HD interface.

Возможности:

4x Lane SAS-3 design compatible to an external miniSAS-HD connector. Easily integrates to existing SAS environments with no additional software. Facilitates the use of common FR4 and other low-cost interconnect materials. Improve Signal Integrity and system rubustness Compatible with link training between host and storage system components. Compatible with OOB signaling in SAS/SATA systems

Документация:
  • Схемотехника
  • BOM
Описание:

Одноканальный источник тактовых импульсов нельзя использовать для тактирования нескольких тактовых входов в высокопроизводительных процессорных устройствах, например, таких как многоядерные ARM Cortex-A15 процессоры 66AK2Ex и AM5K2Ex, так как чрезмерная нагрузка, помехи от рассогласования и шумы негативно влияют на производительность. Однако этого можно избежать, используя несколько источников тактовых импульсов вместо одного. Этот дизайн демонстрирует генерирование тактовых сигналов для семейств 66AK2Ex и AM5K2Ex процессоров Keystone II с ядром ARM Cortex-A15 + DSP и многоядерных ARM процессоров путем использования дерева дифференциальных тактовых сигналов. Дизайн демонстрирует законченное решение для генерации всех необходимых тактовых сигналов для ядер и периферии SoC.

 

Возможности:

  • Дерево дифференциальных тактовых сигналов для многоядерных ARM Cortex-A15 систем на кристалле 66AK2Ex и AM5K2Ex;
  • Использование CDCM6208 для генерации всех необходимых тактовых сигналов, необходимых для ядер и периферии;
  • Графический интерфейс пользователя для управления регистрами;
  • Завершенный системный дизайн с принципиальной схемой, BOM, дизайн файлами и руководству по проектированию аппаратной части.

Документация:
  • Схемотехника
  • BOM
  • Топология платы