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Logistics Robot CPU Board

Описание:
The PMP11328 is a high power density 30A PMBus power supply meeting the Xilinx Ultrascale+ ZU9EG FPGA core rail power specifications for Base Station Remote Radio Unit (RRU) applications. The power supply regulates 0.85V for the core rail at 25A in 55mm x 40mm total power supply PCB area. PMBus capability enables easy programming, and custom configuration of the power supply through on-board Non-Volatile Memory (NVM), as well easy Adaptive Voltage Scaling (AVS), and Voltage Margining. The power supply also enables monitoring of the output voltage, current, and external hot spot temperature through PMBus. Overall ±3% tolerance is met while efficiency is >82%.

Возможности:

12V input, 0.85V/25A PoL in 40mm x 55mm PCB area High efficiency >82% at 0.85V/25A, 500kHz Adaptive Voltage Scaling (AVS), Voltage Margining, and Output Voltage/Current/Temperature monitoring through PMBus and TI's Fusion GUI 4W Power Loss at 12VIN, 0.85V/25A 12mV overshoot/undershoot during a 8A load transient at 10A/µs ±3% total load regulation (AC and DC)

Возможность заказа
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Документация:
  • Схемотехника
  • BOM
Описание:
PMP9335 is designed for Xilinx Zynq FPGA applications utilizing the TPS84A20 and TPS84320. This design uses an external timer to synchronize the switching frequency to 300 kHz. It also employs a controlled power up and power down sequence.

Возможности:

Designed for Xilinx Zynq FPGA applications Compact solution and easy-to-use design with TPS84A20 and TPS84320 buck regulator modules Controlled power up and power down sequence To be used as a “plug in” module, the use of extra bulk capacitance on external pcb is assumed

Документация:
  • Схемотехника
  • BOM
Описание:
The Intel Core i7 power management design is a complete solution for Intel IMVP-7 SVID. A GUI communication program is available along with several test points on the board to evaluate the static and dynamic performance of the CPU's DC/DC Controller. The design features an IMVP-7 3-Phase CPU supply, a 2 Phase GPU Vcore supply, a 1.05VCCIO supply, and a DDR3L/DDR4 memory rail. To greatly improve power density and thermal performance, TI's 5-mm x 6mm NEXFET Power Block MOSFETs are used.

Возможности:

• Design supports a 9-20V input from Vbatt • Small high-density power solution for Ivy Bridge • 3 Phase CPU supply supports up to 94A • 90% peak (80% full-load) efficiency from 12Vin to 1.05Vout - CPU Supply • Low CPU supply ripple: 25mV • Design has been built and tested. Board available.

Документация:
  • Даташит
  • Схемотехника
  • BOM
  • Тестирование
Описание:
Designers can save board space, cost and reduce power consumption by following DDR3 guidelines without VTT termination. This reference design shows how to do that with AM437x. This type of design is not for everyone as there are certain restrictions. Having short trace lengths, a maximum of two DDR3 parts and a balanced T-topology are must-have requirements; otherwise VTT termination guidelines should be followed.

Возможности:

System optimized DDR3/DDR3L design on Sitara AM437x processor with integrated DDR controller Optimized layout requires no VTT termination Two 4-Gbit DDR3 / DDR3L memories Up to 400 MHz clock (DDR-800 data rate) Complete sub-system reference with schematics, BOM, design files and HW User's Guide implemented on a fully assembled board developed for testing and validation.

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Документация:
  • Схемотехника
  • BOM
Описание:
The Sitara AM437x simplified power sequence feature provides flexibility to power designers. This reference design implementation is a BOM-optimized discrete power solution for the AM437x processor with a minimal number of discrete ICs and basic feature set. The solution represents a baseline of a discrete power solution that can be extended for additional features and capabilities of the AM437x processor.

Возможности:

Simplified, BOM-optimized discrete power solution for the Sitara AM437x processor. AM437x includes an integrated LDO that simplifies processor power sequencing requirements. Systems without controlled power down can greatly benefit from this feature since the integrated LDO always ensures power up/down sequencing is met for VDDS and VDDSHVx supplies The TLV62565 step down converter provides the 3.3 volt supply and the TLV62080 provides the 1.1 volt supply. Two TLV702xx low drop out regulators (LDOs) provide the 1.5-V and 1.8-V supplies. TLV803M voltage supervisor keeps the processor in reset until all rails are operational and to reset the processor when input power is lost. This design is tested and includes schematics, BOM, design guide, and test data.

Документация:
  • Схемотехника
  • BOM
Описание:
PCI-Express provides for low pin-count, high reliability, and high-speed with data transfer at rates of up to 5.0 Gbps per lane, per direction, and an PCIe module is included on the TI 66AK2G02 DSP + ARM Processor system on chip (SoC). This PCIe PCB design considerations reference design helps developers optimize the printed circuit board (PCB) design by providing best-practice PCB for the PCIe portion of the 66AK2G02 Processor SoC. This in turn enables developers achieve desired PCIe signal performance on the first PCB implementation pass, allowing rapid focus on K2G Processor based application development and test. The 66AK2G02 General Purpose EVM (EVMK2G) is used as a reference to discuss some of these considerations.

Возможности:

Optimized High Speed Signal Routing Surface-Mount PCIe x1 Socket Example of AC Coupling Capacitor Placement Example of Recommended Differential Pair Spacing

Документация:
  • Схемотехника
  • BOM
Описание:
The TIDEP0070 reference design describes system considerations for Dual Data Rate (DDR) memory interface with Error Correcting Code (ECC) support in high-reliability applications, based on the 66AK2G02 Multicore DSP + ARM processor System-on-Chip (SoC). It enables developers to implement a high reliability based solution rapidly by discussing system interfaces, board hardware, software, throughput performance and diagnostic procedures.
Возможности:

Optimized high speed signal routing Surface-mount PCIe x1 socket Example of AC coupling capacitor placement Example of recommended differential pair spacing

Документация:
  • Схемотехника
  • BOM