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Pulse, Data & Pattern Generators

Описание:
Using the THS3091 high voltage, low distortion current-feedback op amp, this reference design showcases the technique and the benefits of configuring multiple op-ampsin a load sharing configuration when driving high voltage signals into heavy loads. Supported by a full scale application report, the design can be easily adjusted for a given application.

Возможности:

15V supply voltage Up to 24VPP output swing Third-Harmonic Distortion of 32dBc when driving a 20VPP, 70MHz sine wave into a 100Ω load (double-terminated 50Ω cable) Second-Harmonic Distortion of 38dBc when driving a 20VPP, 70MHz sine wave into a 100Ω load (double-terminated 50Ω cable) High Current Drive Capability (up to 400mA with two THS3091 op amps) This reference design has been lab tested and is supported with design files and a design guide

Документация:
  • Схемотехника
  • BOM
  • Тестирование
Описание:
This design shows how to use an active interface with the current sink output of the DAC5682Z - typical applications for this include front ends for arbitrary waveform generators. The EVM includes the DAC5682Z for digital-to-analog conversion, an OPA695 to demonstrate an active interface implementation using a wide bandwidth operational amplifier and a THS3091 and THS3095 to showcase an operational amplifier with large voltage swing. Also included on board are a CDCM7005, VCXO and Reference for clock generation, and linear regulators for voltage regulation. Communication to the EVM is accomplished via a USB interface and GUI software.

Возможности:

Example of a high performance arbitrary waveform generator front end Wideband signal generation using DAC5682z Provide 1 wideband high performance output capable of driving 50 ohm loads using OPA695 Provide a high voltage output using the THS3095 with a maximum of 30Vpp Easy evaluation platform using TSW1400 and HSDC Pro pattern generator software

Документация:
  • Схемотехника
  • BOM
  • Топология платы
Описание:
In TIDA-00684 reference design a quad-channel TSW3080 evaluation module (EVM) is developed to shows how to use an active amplifier interface with the DAC38J84 to demonstrate an arbitrary-waveform-generator frontend. The DAC38J84 provides four DAC channels with 16 bits of resolution with a maximum update rate of 2.5 GSPS. The THS3217 provides a wideband differential-to-single-ended output. The THS3095 provides a high dynamic range output of up to 26 VP-P. The LMH5401 provides a very wideband differential output. All of these paths provide a DC-coupled interface with the ability to drive 50 Ω at a high-performance level. The design also includes a reference transformer path for comparison purposes.
Возможности:

Wideband (500 MHz), DC-coupled active interface, capable of 5 Vp-p signal swing 50 MHz passband channel capable of 26 Vp-p signal swing Wideband (1.0 GHz), DC-coupled signal path All channels optimized for driving 50 ohms impedance loads Available onboard clocking with an option for external clocking

Документация:
  • Схемотехника
  • BOM
Описание:
To further increase the range, data rate, and reliability of modern mobile communications systems, system designers continue to place more emphasis on multiple-antenna transmitter systems to achieve combinations of spatial diversity and spatial multiplexing. Such implementations can further compensate for path loss and the multipath effect of transmission mediums. These implementations can also potentially increase range and data rate and improve reliability. Multiple-antenna systems with beamforming techniques also allows for better focus of transmitter energy and the system can potentially reduce the size of an antenna while increasing the transmitter range. More mobile communications systems and radar systems are starting to adopt multiple-antenna transmitters in their designs. For such multiple-antenna transmitter implementations, each individual transmitter requires digital-to-analog converters (DACs) for the digital bits to RF transmission. Multiple transmitters and the associated antenna must also be synchronized in time. The design may utilize JESD204B subclass 1 type DAC3xJ8x, which has the capability to achieve multiple DAC3xJ8x device synchronization. The DAC3xJ8x is a high-speed 16-bit DAC with up to 2.8 GSPS of sample rate. All of the capabilities of DAC3xJ8x simplify device synchronization and facilitate the design of a multiple-antenna transmitter system.

Возможности:

High-Speed Data Transfer High Sample Rate Digital-to-Analog Conversion JESD204B Subclass 1 Support Multi-Device Synchronization Synchronized Clock Distribution

Документация:
  • Схемотехника
  • BOM
  • Топология платы
Описание:
For wideband receiver system developers currently using FPGA or ASIC to connect High Speed data converters to a baseband processor, who need faster time to market with increased performance and significant reduction in cost, power, and size. This reference design includes the first widely available processor integrating a JESD204B interface and Digital Front End Processing (DFE). Connecting ADC32RF80 to DAC38J84 provides an efficient solution for avionics and defense, test and measurements and industrial applications.
Возможности:

Easy integration of signal processor to data converters over JESD204B Usable bandwidth of two 75MHz channels or a single 100MHz channel when connected to ADC32RF80 DFE processing for filtering, down-sampling or up-sampling: FFTC hardware accelerator to offload comput-intensive 2D FFT operation, achieving low latency and high accuracy Wideband sampling with JESD attached signal processing solution including Digital Signal Processor (DSP), ADC and DAC boards, demo software, configuration GUIs and getting started guide A robust demonstration and development platform including three EVMs, a deterministic latency card, schematic, BOM, user guide, benchmarks, software and demos

Документация:
  • Схемотехника
  • BOM
Описание:
This TI Reference Design provides the theory, component selection, and simulation of a single supply comparator required to use AC coupling to detect sine waves or square waves. Often this is needed due to differences in ground between two different modules. Whenever AC coupling is involved into single supply circuitry negative voltages become a concern. Excessive negative voltages on comparators can cause the comparator to trip erroneously or to stay stuck at unpredictable levels. Proper high pass filtering and DC offsetting are required for reliable operation. This design will show how to AC couple a wide range of input signal levels and frequencies into a high speed comparator to generate a robust and accurate clock signal. See more TI Precision Designs

Возможности:

AC Couples Pulses to eliminate Ground Potential Differences Comparator Outputs 0V to 5V Single-Supply Solution Input Frequency from 2kHz to 32MHz, 40% to 60% duty cycle Utilizes TLV3501 for fast response time Utilizes Offset and Filter for reliable Single Supply Operation This Precision Reference Design Includes Theory Component Selection TINA-TI Simulation Modification Options

Документация:
  • Даташит
  • Схемотехника
  • BOM
  • Топология платы
Описание:

Данный протестированный проект TI представляет собой фильтрующий инвертирующий аттенюатор на -40 dB. Данная схема выдаёт отфильтрованный, инвертированный и ослабленный сигнал, получаемый из несбалансированного входного сигнала и используемый для тестирования и измерений, а также для других применений в области генерирования формы сигнала. Для инвертирования, ослабления и фильтрации входного сигнала используется один малошумящий ОУ OPA1611. За счёт низкого уровня шумов и искажения сигнала OPA1611 обеспечивается получение точных и чистых выходных сигналов.

Возможности:

  • Отфильтрованный выходной сигнал на уровне -40 dB
  • Точность 0,1 dB
  • Выход с OPA1611 с низким уровнем шумов
  • Данный протестированный проект включает в себя теоретический материал, анализ подбора компонентов, симуляцию TINA-TI, схемы электрические принципиальные и трассировку печатной платы, результаты измерений, а также возможности модификации проекта

Возможность заказа
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Документация:
  • Даташит
  • Схемотехника
  • BOM
  • Топология платы
Описание:

Архитектура R-2R ЦАП имеет хорошие характеристики в части шумов и точности, но за счёт больших всплесков напряжения при смене кода. Данный проект преследует цель уменьшения всплесков напряжений, возникающих при особых изменениях кода в архитектуре R-2RЦАП. В данном проекте эти всплески уменьшаются, что делает возможным его применение в системах, чувствительных к всплескам напряжений (например, в генераторах формы сигналов).

Возможности:

  • 18-битный выход 0-5 В
  • Схема с R-2R ЦАП с уменьшением всплесков напряжений с помощью устройства хранения и выборки
  • Общая нескорректированная ошибка менее 0,15 % во всём диапазоне измерений
  • Интегральная нелинейность (INL) менее 2 наименьших значащих битов (LSB)

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Документация:
  • Даташит
  • Схемотехника
  • BOM
  • Топология платы